The present application relates generally to an improved data processing apparatus and method and more specifically to an on-chip non-volatile storage of a test-time profile for use in efficiency and performance control of the chip resources.
Microprocessor chip reliability and efficiency are of primary importance in current processor design. Increasingly, sophisticated on-chip resource management units, controllers, and storage units are dedicated to improve the chip efficiency and reliability at runtime. Most of these on-chip controllers and dedicated resource management units start with the basic assumption that the underlying chip hardware is ideal, or so close to ideal that it can be safely assumed to be ideal. However, there are a number of research studies that indicate that this assumption is far from reality.
Most chips exhibit significant variation in the form of performance variation, power consumption, and temperature variation, as well as differences in operating corners and the like. Since the on-chip resource management units are oblivious to such variations, they are not fully capable of improving efficiency and reliability of the on-chip resources. That is, the on-chip resource management units assume that all of the computational cores, processors, and/or functional units operate identically across the chip.
For example, if a chip has inherent heating tendencies in a set of computational cores, e.g., due to increased leakage power, process variation (differences in the operation of a core due to variations in the manufacturing or forming of the core), or the like, such inherent heating tendencies are not taken into account by the on-chip resource management units. To the contrary, because the on-chip resource management units are oblivious to such inherent tendencies, the heating causes undesirable hot-spots to be generated on the chip.
There are various tests that are utilized at the manufacturer site to profile the on-chip resources including corner tests for multi-core architectures, functional tests, etc. The information gathered during such tests is not stored to improve the efficiency of the chip during regular operation, however. To the contrary, these tests are typically used to determine whether a chip passes or fails in order to determine whether the chip needs to be discarded or not. Moreover, this information is not stored for improved efficiency because there are major complications with the flow of this information. For example, chip manufacturers may be unwilling to provide such information since it may indicate weaknesses of the chip. Moreover, there has been no real appreciation of the potential use of such information during operation of the chip. Furthermore, even if the information flow were more free, the on-chip resource management units do not having the ability to maintain such information when the chip is powered down.